Electronic Resource

Multicore systems on-chip : practical software/hardware design

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System on chips designs have evolved from fairly simple unicore, single memory designs to complex heterogeneous multicore SoC architectures consisting of a large number of IP blocks on the same silicon. To meet high computational demands posed by latest consumer electronic devices, most current systems are based on such paradigm, which represents a real revolution in many aspects in computing. The attraction of multicore processing for power reduction is compelling. By splitting a set of tasks among multiple processor cores, the operating frequency necessary for each core can be reduced, allowing to reduce the voltage on each core. Because dynamic power is proportional to the frequency and to the square of the voltage, we get a big gain, even though we may have more cores running. As more and more cores are integrated into these designs to share the ever increasing processing load, the main challenges lie in efficient memory hierarchy, scalable system interconnect, new programming paradigms, and efficient integration methodology for connecting such heterogeneous cores into a single system capable of leveraging their individual flexibility. Current design methods tend toward mixed HW/SW co-designs targeting multicore systems on-chip for specific applications. To decide on the lowest cost mix of cores, designers must iteratively map the device’s functionality to a particular HW/SW partition and target architectures. In addition, to connect the heterogeneous cores, the architecture requires high performance complex communication architectures and efficient communication protocols, such as hierarchical bus, point-to-point connection, or Network-on-Chip. Software development also becomes far more complex due to the difficulties in breaking a single processing task into multiple parts that can be processed separately and then reassembled later. This reflects the fact that certain processor jobs cannot be easily parallelized to run concurrently on multiple processingcores and that load balancing between processing cores – especially heterogeneous cores – is very difficult.

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Ketersediaan

Informasi Detail

Judul Seri

Atlantis Ambient and Pervasive Intelligence (ATLANTISAPI, volume 7)

No. Panggil

E1544

Penerbit

Paris : Atlantis Press., 2013

Deskripsi Fisik

xxvi, 273 hlm. : il. warna.

Bahasa

English

ISBN/ISSN

9789491216923

Klasifikasi

NONE

Tipe Isi

text

Tipe Media

computer

Tipe Pembawa

online resource

Edisi

-

Subjek

Desain Perangkat Lunak : Teknik Informatika
Ilmu Komputer : Chip Multicore
Sistem Multicore : Perangkat Keras (Hardware)

Info Detail Spesifik

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Pernyataan Tanggungjawab

Abderazek Ben Abdallah

Versi lain/terkait

Lampiran Berkas

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